SoC Physical Integration Engineer
Core
Define and develop flows for chip-level integration, design/verify/integrate FPGA/ACAP sub-blocks, and execute physical and electrical verification for AMD SoC devices.
Role type
Senior IC SoC Physical Integration Engineer
Builds
High-performance, energy-efficient processors and adaptive computing technologies for edge computing solutions
Domain
Semiconductor / Hardware Design / Physical Implementation
Required skills
FPGA architecture, advanced process nodes (2nm/3nm), 2.5D/3D interposer technologies, physical design tools (Virtuoso, ICC2, Fusion Compiler, Innovus), circuit design (SPICE, Verilog), Place and Route (P&R), scripting (Perl, Python, TCL, C-shell), Unix/Linux environments
Preferred skills
Cross-functional collaboration, debugging, analytical problem-solving
Technologies
Virtuoso, ICC2, Fusion Compiler, Innovus, SPICE, Verilog, Perl, Python, TCL, C-shell, Make, Unix/Linux
Responsibilities
Define and develop flows and methodologies for chip-level integration; Develop tools and automation to enhance design verification and engineering efficiency; Design, verify, and integrate FPGA/ACAP sub-blocks; Coordinate activities across design teams; Execute chip-level physical verification; Execute chip-level electrical verification
Seniority
Senior, hands-on IC
