PD Lead
Core
Lead physical verification sign-off, full-chip integration, and packaging interface planning for advanced SoC programs.
Role type
Senior IC physical verification lead (SoC integration)
Builds
Advanced System-on-Chip (SoC) designs for AMD processors
Domain
Semiconductor / Physical Design / Physical Verification
Required skills
DRC, LVS, ERC, antenna checks, GDS assembly, hierarchical LVS reconciliation, RDL planning, bump mapping, foundry rule deck management, tapeout execution, cross-functional leadership, automation scripting (TCL/Python)
Preferred skills
Full-chip SoC integration, advanced packaging flows (flip-chip, 2.5D, 3D-IC), IR/EM, SI/PI, PEX, reliability checks
Technologies
Calibre, ICV, Pegasus, TCL, Python
Responsibilities
Drive end-to-end DRC/LVS/ERC closure at block and full-chip level; Lead top-level integration of IPs/macros into SoC; Define RDL planning and bump mapping strategy; Own sign-off checklist and tapeout readiness; Lead debug of complex DRC violations and LVS mismatches; Mentor PHY-V engineers and interface with PD, Analog, and Packaging teams
Seniority
Senior, hands-on IC
