Senior IC Layout design Engineer
Core
Senior analog/mixed-signal layout design engineer responsible for high-speed SerDes circuit implementation and team supervision.
Role type
Senior IC layout design engineer (SerDes)
Builds
High-performance SerDes analog mixed-signal circuits for AMD CPU and GPU products
Domain
Semiconductor / Analog Mixed-Signal IC Design
Required skills
High-speed layout design, Floor-planning, Power distribution network design, Clock and signal routing, Transistor level layout, Post-layout circuit performance analysis, Block/IP/chip level integration, Schedule estimation, Layout methodology definition, Layout productivity improvement (PCell development), Supervision of layout resources, Quality issue assessment
Preferred skills
Lower process nodes (7nm or below), Analog and mixed-signal layout fundamentals (IR, EM, capacitances, RC delay), High-speed critical signal routing and shielding, Physical design verifications (LVS/DRC/ERC/ANT/ESD), Circuit design concepts and IC manufacturing processes, High-speed SerDes blocks and PLLs in Fin-FET, Digital on top integration flow or digital SOC flow, Cadence SKILL and programming (Perl, Python, Tcl)
Technologies
Cadence SKILL, Perl, Python, Tcl, Fin-FET, CMOS
Responsibilities
Layout design of high speed and high performance SerDes analog mixed signal circuit, Block level physical implementation including floor-planning and routing, Participate in post-layout circuit performance analysis, Participate in block/IP/chip level integration activities, Estimate realistic schedule and track progress, Define layout methodology and flow, Supervise layout resources and assess quality issues
Seniority
Senior, hands-on IC with supervisory role