Physical Design Engineer
Core
Senior Silicon Design Engineer responsible for driving Electromigration and IR Drop (EMIR) analysis, debug, and signoff closure for complex, high-performance SoC designs.
Role type
Senior IC physical design engineer (EMIR/PDN)
Builds
High-performance ASIC/SoC chips
Domain
Semiconductor / VLSI / Power Integrity
Required skills
EMIR analysis, IR drop analysis, power grid validation, root cause analysis, design flow automation, cross-functional collaboration, Python/Tcl/Perl/Shell scripting, LEF/DEF/parasitics handling
Preferred skills
Ansys RedHawk-SC, Cadence Voltus, multi-voltage designs, bump planning, package power integrity, hierarchical EMIR analysis, advanced-node SoC experience
Technologies
Ansys RedHawk-SC, Cadence Voltus, Python, Tcl, Perl, Shell, LEF, DEF
Responsibilities
Perform static and dynamic IR-drop and Electromigration analysis, develop and validate EMIR flows, perform power-grid validation, identify weak-grid regions and violations, perform root-cause analysis of EMIR issues, collaborate with Physical Design teams for power-grid optimization, drive assigned blocks toward EMIR signoff, develop automation for EMIR flow execution.
Seniority
Senior, hands-on IC
