Senior Mask Design Engineer - Hardware
Core
Senior Mask Layout Design Engineer creating physical layouts for mixed-signal functions, high-speed datapaths, and clocking designs in sub-micron CMOS technologies for chiplet interface projects.
Role type
Senior IC mask layout design engineer
Builds
Chiplet interface projects and VLSI products
Domain
Semiconductor hardware design (mixed-signal, FinFET)
Required skills
Mixed-signal layout design, FinFET technology, Cadence Virtuoso, DRC/LVS flows, floor planning, high-speed clocking design
Preferred skills
Perl, Python, SKILL scripting
Technologies
Cadence Virtuoso, Cadence tools, FinFET, CMOS
Responsibilities
Perform physical layout for mixed-signal functions, work with mixed-signal design engineers to customize designs for integration, take part in floor planning and custom layout, verify against design rules and schematics
Seniority
Senior, hands-on IC
