Senior Mask Layout Design Engineer
Core
Perform physical layout for high-speed mixed-signal circuit functions (PLLs, high-speed I/O, ESD structures) in sub-micron CMOS technologies.
Role type
Senior IC mask layout design engineer
Builds
VLSI products integrating mixed-signal and ASIC designs
Domain
Semiconductor manufacturing / Analog & Mixed-Signal IC design
Required skills
Mixed-signal circuit layout, Floor planning, DRC/LVS verification, Cadence Virtuoso, FinFET technology, Perl/Python scripting
Preferred skills
TSMC N5/N4/N3 process, High-speed SerDes/RF layout, Top-level integration, MSEE degree
Technologies
Cadence Virtuoso, ICV/Calibre, Perl, Python, TSMC FinFET
Responsibilities
Perform physical layout for mixed-signal functions, Work with ASIC engineers to customize designs for integration, Verify layouts against design rules and schematics
Seniority
Senior, hands-on IC
