Senior Analog Layout Design Engineer
Core
Perform physical layout for high-speed mixed-signal circuits (PLLs, SerDes, I/O, ESD) in sub-micron CMOS FinFET technologies.
Role type
Senior IC analog layout engineer
Builds
VLSI products integrating mixed-signal functions
Domain
Semiconductor / Analog IC Design
Required skills
Analog circuit layout in submicron CMOS/FinFET, Cadence Virtuoso, DRC/LVS verification, EM/IR analysis, Floor planning, Mixed-signal circuit design (Op-Amps, ADC/DACs)
Preferred skills
Python scripting, Custom DRC/LVS deck creation
Technologies
Cadence Virtuoso, ICV, Calibre, Python
Responsibilities
Perform physical layout for mixed-signal functions, Work with ASIC and mixed-signal engineers to customize designs, Verify layouts against design rules and schematics, Run and debug DRC and LVS, Perform EM/IR analysis
Seniority
Senior, hands-on IC
