Senior Package Layout Engineer
Core
Designing state-of-the-art high-speed interconnect systems for ASIC packages in supercomputers and datacenters.
Role type
Senior IC Packaging Design Engineer
Builds
High-speed and PDN design for ASIC packages
Domain
Semiconductor / High-speed Interconnect
Required skills
Package/PCB layout, high-speed signal integrity, substrate routing, placement, stack-up, power distribution, Cadence APD (Allegro), SiP tools, pin-out optimization, manufacturing process knowledge
Preferred skills
Ansys (SIwave, HFSS), Cadence (Sigrity, PowerSI), Skill language, Python/Perl/Shell scripting
Technologies
Cadence Virtuoso, Cadence APD, Allegro, SiP, Ansys SIwave, Ansys HFSS, Sigrity, PowerSI
Responsibilities
Implement high-speed and PDN design for ASIC packages, Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, power distribution, Optimize package pin out incorporating system level trade-offs, Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations, Collaborate with SI/PI/HW design teams and product teams
Seniority
Senior, hands-on IC
