Senior Mask Layout Design Engineer
Hybrid
Core
Perform physical layout for mixed-signal functions like PLLs, high-speed I/O circuits, and ESD structures in sub-micron CMOS technologies.
Role type
Senior IC mask layout design engineer
Builds
VLSI products integrating ASIC and mixed-signal circuits
Domain
Semiconductor / Analog IC design
Required skills
Cadence Virtuoso, DRC/LVS verification, floor planning, sub-micron CMOS layout, Perl/Python scripting
Preferred skills
Custom DRC/LVS deck creation, mixed-signal circuit integration
Technologies
Cadence Virtuoso, Dracula, Hercules, Calibre, Primeyield, Perl, Python, Skill
Responsibilities
Perform physical layout for mixed-signal functions; Work with ASIC and mixed-signal engineers to customize designs; Execute floor planning, custom layout, and verification against design rules and schematics
Seniority
Senior, hands-on IC
