Senior STA Signoff Methodology Engineer
Core
Drive sign-off strategies for GPUs, CPUs, LPUs, and SoCs by optimizing performance, yield, and reliability through advanced modeling, analysis, and automation.
Role type
Senior STA Signoff Methodology Engineer
Builds
Next-generation AI computing platforms (GPUs, CPUs, LPUs, SoCs)
Domain
Semiconductor / ASIC Design / Advanced Node Physics
Deliverable
production ML models
Required skills
SPICE simulation, STA methodologies, RC extraction, device physics, Python, JMP, Tcl, C++, EDA tools (PrimeTime, ICC2, RedHawk, Tempus), low-power techniques, signal/power integrity, 3nm+ technology nodes
Preferred skills
3D IC integration, die stacking, packaging, self-heating modeling, data analysis
Technologies
Python, JMP, Tcl, C++, PrimeTime, ICC2, RedHawk, Tempus
Responsibilities
Run large-scale SPICE simulations and STA experiments; Develop STA and PNR flows addressing aging, self-heating, thermal effects, IR drop, and electromigration; Collaborate with design teams to define timing-signoff strategies; Develop tools to improve design predictability and silicon reliability; Perform data analysis to improve STA-to-silicon correlation
Seniority
Senior, hands-on IC
