Senior Mask Design Engineer - Hardware
Hybrid
Core
Performing physical layout for mixed-signal functions including top-level, high-speed datapaths, and clocking designs in sub-micron CMOS technologies.
Role type
Senior IC mask layout design engineer (mixed-signal)
Builds
Chiplet interface projects and VLSI products
Domain
Semiconductor hardware design (mixed-signal, FinFET)
Required skills
Mixed-signal layout design, FinFET technology, Cadence Virtuoso, DRC/LVS flows, floor planning, Perl/Python scripting
Preferred skills
Custom deck customization, fast-paced iteration
Technologies
Cadence Virtuoso, Perl, Python, Skill
Responsibilities
Create high-quality layouts independently, customize designs for integration, verify against design rules and schematics
Seniority
Senior, hands-on IC
