Senior Power Integrity Co-Design Engineer
Core
Architect and deliver di/dt mitigation across silicon, package, board, and platform to meet product noise targets. (via careerplan.io/jobs/893395803704-senior-power-integrity-co-design-engineer-at-nvidia)
Role type
Senior IC power integrity co-design engineer
Builds
Next-generation silicon power delivery features and mitigation IP for high-performance processors
Domain
Semiconductor / Power Integrity / PDN
Deliverable
production ML models | product features
Required skills
di/dt analysis and mitigation, voltage droop management, PDN design (die/package/board), transient noise analysis, decap budgeting, voltage regulator response, Sim-to-Si correlation, system-level trade-off analysis
Preferred skills
ML/AI application to noise modeling, multi-rail multi-domain PDN ownership, toolchain development, GPU/CPU/AI accelerator silicon experience
Technologies
Scopes, probes, DAQ, simulators, AI tools
Responsibilities
Architect voltage-noise mitigation across the full stack, co-design noise features with cross-functional teams, define and sign off product-level voltage noise targets, build Sim-to-Si correlation methodology, model and prototype next-gen noise features, lead critical noise bug resolution during bringup
Seniority
Senior, hands-on IC
