Senior Signal Integrity Engineer – LPU Packaging
Core
Lead signal integrity design, simulation, and correlation for high-speed SerDes channels across die, package, board, and system boundaries for next-generation HPC and AI platforms.
Role type
Senior IC signal integrity engineer (advanced packaging)
Builds
Robust high-speed interconnect solutions for data center and AI systems
Domain
Semiconductor packaging, high-speed digital design, HPC
Required skills
High-speed SerDes design and analysis, Electromagnetics and transmission line theory, Channel modeling and S-parameter analysis, IBIS-AMI flows, Time/frequency-domain analysis, NRZ and PAM4 signaling, Equalization techniques, Jitter/noise mechanisms, End-to-end channel budgeting, Simulation-to-measurement correlation
Preferred skills
PCIe, CXL, NVLink, Ethernet interface experience, Advanced packaging structures and substrate technologies, Chip-package-board co-design, SI signoff methodology development, Mixed-domain tradeoffs (SI/PI/thermal/mechanical)
Technologies
Ansys HFSS, SIwave, Cadence Sigrity, ADS, HSPICE, VNA, TDR, Oscilloscope
Responsibilities
Lead SI design and analysis for high-speed SerDes channels, Develop simulation flows for 2.5D/3D/multi-die integration, Build chip-package-board co-simulation methodologies, Perform pre/post-layout SI analysis and review layouts, Correlate simulation with lab measurements, Support interface bring-up and debug, Automate SI analysis and data processing
Seniority
Senior, hands-on IC
