Senior Mask Design Engineer - Hardware
Core
Senior Mask Layout Design Engineer performing physical layout for high-speed mixed-signal circuits (PLLs, SerDes, ADCs, ESD) in sub-micron CMOS technologies.
Role type
Senior IC Mask Layout Design Engineer
Builds
High-speed mixed-signal circuit designs for VLSI products
Domain
Semiconductor / Analog IC Design
Required skills
Mask and Layout Design, Analog circuit layout concepts, Cadence Virtuoso, DRC/LVS checking flows, Scripting (Perl, Python), Verification tools (Dracula, Hercules, Calibre, Prime-yield)
Preferred skills
Cross-functional collaboration, Teamwork
Technologies
Cadence Virtuoso, Dracula, Hercules, Calibre, Prime-yield, Perl, Python
