Senior Mask Design Engineer - Hardware
Core
Senior Mask Layout Design Engineer performing physical layout for high-speed mixed-signal circuits (PLLs, SerDes, ADCs) in sub-micron CMOS technologies.
Role type
Senior IC mask layout design engineer
Builds
High-speed mixed-signal circuit designs for VLSI products
Domain
Semiconductor / Analog IC Design
Required skills
Mixed-signal circuit layout, Cadence Virtuoso, DRC/LVS flows, Perl/Python scripting, Verification tools (Dracula, Hercules, Calibre, Primeyield)
Preferred skills
Floor planning, Custom layout, Cross-functional collaboration
Technologies
Cadence Virtuoso, Calibre, Primeyield, Dracula, Hercules, Perl, Python
Responsibilities
Perform physical layout for mixed-signal functions, work cross-functionally with ASIC engineers, take part in floor planning and custom layout, verify against design rules and schematics
Seniority
Senior, hands-on IC
