GPU/SOC Low-Power Feature Architect
Core
Architecting next-gen high-speed interconnects (NVLink, NVLink-C2C) and optimizing IO power efficiency for GPU and AI products.
Role type
Senior IC hardware architect (interconnects & power)
Builds
High-speed IOs, interconnect topologies, and power-optimized silicon features for AI, graphics, and autonomous driving.
Domain
Semiconductor hardware design, high-speed interconnects, power management
Deliverable
production ML models
Required skills
System-level power management, silicon/platform power modeling, high-speed interface design, timing analysis, computer architecture, firmware/driver interaction understanding, debug of HSIO bugs
Preferred skills
Capacity planning, use case analysis, perf/power modeling, leadership across engineering teams
Technologies
NVLink, NVLink-C2C, mixed-signal design, DGX platforms
Responsibilities
Design next-generation high-speed IOs; optimize IO power and energy efficiency; ensure interoperability in complex interconnect topologies; debug technically challenging HSIO bugs; collaborate with system architects, mixed-signal teams, and software/firmware groups.
Seniority
Senior, hands-on IC
