Physical Design Backend STA Engineer
Core
Perform advanced Static Timing Analysis (STA) at chiplet and FC level for high-speed communication devices, ensuring timing convergence and quality approval from pre-layout to signoff.
Role type
Senior IC physical design STA engineer
Builds
High-speed communication chips (Networking team)
Domain
Semiconductor / Hardware Design
Required skills
Static Timing Analysis (STA), Prime Time, SDC generation, timing path debugging, chiplet design, FC (Flip-Chip) level analysis, physical design convergence, RTL/DFT collaboration
Preferred skills
Physical build flows (PNR, STA, physical verification), advanced STA methodologies
Technologies
Prime Time, SDC, Chiplet, FC
Responsibilities
Perform advanced STA at chiplet and FC level; Review and debug timing paths and understand constraints; Identify convergence risks and collaborate with physical design, RTL, and DFT teams; Responsible for full timing closer and quality approval from pre-layout to signoff.
Seniority
Mid-level, hands-on IC
