Senior Mask Layout Design Engineer
Core
Senior Mask Layout Design Engineer performing physical layout for digital and mixed-signal functions (clock generators, op-amps, sensors, security circuits, power delivery) in sub-micron CMOS technologies.
Role type
Senior IC mask layout design engineer
Builds
ASIC and mixed-signal VLSI products
Domain
Semiconductor / Analog & Mixed-Signal IC Design
Required skills
Physical layout design in sub-micron CMOS, Cadence Virtuoso, DRC/LVS verification (Dracula, Hercules, Calibre), Floor planning, Perl/Python scripting, Foundry interaction, Mentoring junior designers
Preferred skills
Layout automation knowledge, Knowledge of layout automation
Technologies
Cadence Virtuoso, Dracula, Hercules, Calibre, Perl, Python
Responsibilities
Perform physical layout for digital and mixed-signal functions, Floor planning and custom layout, Verify against design rules and schematics, Fill, post-processing, DRC mitigation, Foundry interactions, Mentor junior mask designers
Seniority
Senior, hands-on IC
