Senior Package Layout Engineer
Core
Designing high-speed interconnect systems and IC substrates for Supercomputers and Datacenters.
Role type
Senior IC Packaging Design Engineer
Builds
ASIC packages and high-speed interconnect systems
Domain
Semiconductor / IC Packaging
Required skills
Package layout, PCB layout, high-speed signal integrity, PDN design, substrate routing, placement, stack-up, power distribution, APD tools, SiP tools, wire bond, flip chip packages
Preferred skills
Ansys SIwave/HFSS, Cadence Sigrity/PowerSI, Skill language, Python/Perl/Shell scripting
Technologies
APD, SiP, Ansys, Cadence
Responsibilities
Implement high-speed and PDN design for ASIC packages, Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, power distribution, Optimize package pin out incorporating system level trade-offs, Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations, Collaborate with SI/PI/HW design teams and product teams, Plan and lead projects from start to finish
