Staff ASIC STA Engineer
Core
Lead ASIC physical STA design and engineering workflow development for multimodal generative AI inference acceleration products.
Role type
Staff ASIC STA Engineer (Individual Contributor Tech Lead)
Builds
Full-chip timing closure and signoff flow for custom silicon HPC chips
Domain
Semiconductor / VLSI / Generative AI Hardware
Deliverable
production ML models
Required skills
Hierarchical STA, Clock methodology, SDC writing for high-speed IP (PCIe, SerDes), Genus/Innovus tool usage, Timing ECO generation, EDA tool expertise (Cadence/Synopsys PrimeTime/Tempus)
Preferred skills
Multi-disciplinary engineering background, Passion for generative AI, Creative EDA solutions
Technologies
Cadence, Synopsys, Genus, Innovus, PrimeTime, Tempus
Responsibilities
Guide and assist colleagues to improve frontend physical design with respect to STA, Drive optimization and timing exploration workflows, Innovate and improve scalable high-performance systems and tools, Work closely with ASIC team members to understand and improve workflows and EDA needs
Seniority
Staff, hands-on IC tech lead
