Senior ASIC Physical Design Engineer
Core
Lead ASIC front-end physical design and engineering workflow development for multimodal generative AI inference acceleration products.
Role type
Senior IC ASIC Physical Design Engineer
Builds
Custom silicon hardware for generative AI inference systems
Domain
Semiconductor / VLSI / Generative AI
Deliverable
production ML models
Required skills
ASIC physical design workflows, EDA tools (Cadence/Synopsys), power analysis, clock methodology, STA analysis, DRC/LVS, metal fill, backend design support
Preferred skills
Front-end optimization, full-chip timing analysis, workflow innovation
Technologies
Cadence, Synopsys, Genus, DC
Responsibilities
Lead front-end physical design and workflow development, guide colleagues on block-level and full-chip design, drive optimization of physical design workflows, collaborate with backend design teams, debug and optimize complex technical challenges
Seniority
Senior, hands-on IC
