Physical Verification Engineer
Core
Ensuring physical design correctness and closure for complex chiplets at advanced nodes (3nm and below) through block and top-level verification.
Role type
Senior IC physical verification engineer (RDL/MIMCAP)
Builds
Production silicon chips for AI, data centers, PCs, gaming, and embedded systems
Domain
Semiconductor / VLSI Design
Required skills
Block-level and top-level physical verification, RDL and MIMCAP closure, low-node technology expertise (3nm and below), Unix/Linux environment, scripting (Tcl, Perl, sed/awk)
Preferred skills
Multi-voltage design verification, Place & Route tools (Fusion Compiler, ICC2, Innovus), sign-off tools (Siemens Caliber), low-power flows (UPF, power-gating, isolation, level-shifter), Python, strong debug capabilities
Responsibilities
Drive RDL and MIMCAP closure for complex chiplets, collaborate with cross-functional teams (Physical Design, RTL Designers), perform block and top-level physical verification, execute electrical checks using FM & VSI
Seniority
Senior, hands-on IC
