Staff Analog Layout Design Engineer
Core
Staff Analog Layout Design Engineer responsible for floor-planning, power grid and signal flow planning, advanced transistor-level layout, and physical/electrical verification of analog, digital, and mixed-signal circuits.
Role type
Staff Analog Layout Design Engineer
Builds
Custom IP blocks and analog/digital/mixed-signal circuits for AMD's product portfolio
Domain
Semiconductor / Analog IC Design
Required skills
Analog layout design, CMOS circuit theory, DRC/LVS/ERC/EMIR/ESD/Latch-up verification, Cadence Virtuoso, Mentor Calibre, floorplanning, power grid planning, signal shielding
Preferred skills
Chip-level integration, ESD concepts, Reliability analysis, clock shielding techniques
Technologies
Cadence Virtuoso, Mentor Calibre
Responsibilities
Complete layout design of analog, digital, and mixed signal circuits; Own major blocks of the custom IP designs; Direct/advise remote and local resources; Schedule and forecast critical assigned blocks; Physical and electrical verification including DRC, LVS, EM/IR, ERC, PERC Latch up and PERC ESD
Seniority
Staff, hands-on IC with mentorship