Lead Staff Engineer, Layout Design
Core
Lead a distributed team designing and developing critical analog, mixed-signal, and custom block layouts for next-generation AI and high-performance computing solutions.
Role type
Senior IC layout design engineering lead
Builds
Analog, mixed-signal, and custom IP blocks (PLL, ADC, DAC, sensors, etc.) for memory and storage products
Domain
Semiconductor manufacturing / VLSI physical design
Required skills
Analog/mixed-signal layout design, LVS/DRC verification, team leadership, project planning, mentorship, IP block expertise (PLL, ADC, DAC), advanced CMOS fundamentals (matching, EM, latch-up, IR drop), tapeout support
Preferred skills
Memory/HBM experience, high-performance computing products, physical design methodologies, scripting (Python, SKILL, Tcl)
Technologies
Cadence VLE/VXL, Mentor Graphics Calibre
Responsibilities
Lead team design of analog/mixed-signal/custom layouts, oversee layout verification (LVS, DRC, Antenna), ensure high-quality block-level delivery, coordinate planning and scheduling for multiple projects, mentor engineers, review sub-block layouts, collaborate with global teams
Seniority
Senior, hands-on IC with management responsibilities
