Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Core
Developing cutting-edge next-generation silicon for deployment in space and ground infrastructures to enable global connectivity via the Starlink network.
Role type
Senior IC full-chip physical verification engineer
Builds
Next-generation silicon chips for Starlink satellites and ground infrastructure
Domain
Semiconductor / Space infrastructure
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Full-chip DRC/LVS/PERC/ESD verification, Foundry DRM interpretation, Advanced node SoC flow development, Scripting (Python/TCL/Perl/Bash), Hierarchical design debugging, Tapeout readiness coordination
Preferred skills
SOC top-level physical design (floor-planning, I/O, bump & RDL), IP integration (SerDes, DDR, analog), Large SoC design experience (>10M gates), AI agent workflow automation
Technologies
Calibre, ICV, Pegasus, Python, TCL, Perl, Bash, Makefile
Responsibilities
Execute full-chip DRC, LVS, ESD, PERC, and antenna signoff; Develop and optimize physical verification flows for advanced node SoCs; Debug complex DRC/LVS violations across hierarchical designs; Perform ESD verification and validate protection strategies; Coordinate signoff across block and top-level teams to drive tapeout readiness; Engage with foundry teams to resolve DRM ambiguities and waiver requests
Seniority
Senior, hands-on IC