Design Verification Engineer - technical lead, Annapurna Labs
Core
Design Verification Engineer leading verification efforts for high-speed I/O and scale-up/out components across the SoC in AWS custom ML accelerators (Inferentia, Trainium).
Role type
Senior IC design verification engineer (technical lead)
Builds
Custom machine learning data center accelerator chips (Inferentia, Trainium)
Domain
Semiconductor / Custom Silicon / Machine Learning Infrastructure
Deliverable
production ML models
Required skills
UVM, constrained-random simulation, testbench development, formal verification, emulation, test-generation tools, AMBA protocols (AHB/APB/AXI), interconnect protocols (PCIe, CXL, UCIe), C/C++, Python/Perl
Preferred skills
Experience verifying at multiple levels of logic (IP blocks to SoCs), object-oriented design, embedded development
Technologies
UVM, formal verification, emulation, test-generation tools, PCIe, CXL, UCIe, AMBA
Responsibilities
Architect and implement end-to-end verification strategies, drive unified verification plans across multiple environments, provide technical leadership and guide architectural decisions, own technical direction for complex verification challenges, guide and mentor team members
Seniority
Senior, hands-on IC with technical leadership