Analog IC Layout Engineer
Core
Designing and verifying physical layouts for mixed-signal and analog circuits in high-bandwidth brain-computer interface SoCs.
Role type
Analog IC Layout Engineer
Builds
Neural recording and stimulation system-on-chip (SoC) for brain-computer interfaces
Domain
Biomedical engineering / Semiconductor design
Deliverable
production ML models | product features | infrastructure
Required skills
Analog and mixed-signal IC layout design, FinFET technology implementation, LVS/DRC/ERC physical verification, circuit floorplan analysis
Preferred skills
Layout automation, P-cell design, analog DFM standards, layout P-cell design, tight matching optimization, low noise and low power consumption optimization
Technologies
SKILL, TCL, Shell, C/C++, Python, FinFET
Responsibilities
Crafting state-of-the-art layouts for amplifiers, filters, switched capacitor circuits, oscillators, data converters, and power management circuits; reviewing layout floorplans and analyzing high-fidelity circuits; performing physical verification of custom IC mask layouts
Seniority
Mid-level, hands-on IC engineer