Senior ASIC RTL Design Engineer, AI Hardware
Core
Design and develop next-generation Cerebras Wafer Scale Engine (WSE) AI chips, focusing on high-performance, power-efficient, and scalable RTL solutions.
Role type
Senior ASIC RTL Design Engineer (AI Hardware)
Builds
Cerebras Wafer Scale Engine (WSE) systems for AI training and inference
Domain
Semiconductor / AI Hardware / High-Performance Computing
Deliverable
production ML models
Required skills
RTL design and integration, Micro-architecture, Functional Specification, Synthesis, Front End Chip integration, Third-party IP integration, Silicon debugging, Networking stack (TCP/IP, RDMA, Ethernet), PCIe/CPU interfaces, Serdes technology, Scripting (Python, TCL)
Preferred skills
FPGA development toolchain (Place and Route, Floor planning, Timing Analysis), Managing external ASIC vendors
Technologies
Python, TCL, FPGA tools
Responsibilities
Drive chip design from functional specification to synthesis; Collaborate with PD, verification, and DFT teams for design closure and coverage; Debug silicon-level functional, timing, and power issues; Work with software/system teams to optimize performance; Integrate third-party IP; Collaborate with external vendors
Seniority
Senior, hands-on IC
