Packaging Architect
Core
Define and execute advanced packaging architecture and roadmap for AI accelerator chips, ensuring high-performance integration of silicon, substrate, and optics.
Role type
Senior IC packaging architect (advanced packaging)
Builds
High-performance AI accelerator systems (DX-1 and future variants)
Domain
Semiconductor hardware / AI infrastructure
Deliverable
production ML models
Required skills
Advanced semiconductor packaging architecture, 2.5D/3D integration, ASIC-to-substrate design, PI/SI simulation, substrate design, team leadership, vendor management
Preferred skills
AI accelerator experience, wafer-level packaging, optical integration, failure analysis
Technologies
Cadence Allegro X APD, Siemens Xpedition, Ansys SIwave, Cadence Sigrity
Responsibilities
Own package architecture and design for ASIC-to-substrate integration; Lead development of 2.5D and 3D package architectures; Define package structures meeting electrical, thermal, and reliability requirements; Own or direct the full package design flow from concept to release; Establish packaging engineering capability and build/lead a team; Collaborate with ASIC, optics, and mechanical engineers; Support manufacturing readiness and DFM/DFX activities
Seniority
Senior, hands-on IC with architectural ownership
