Junior Digital Verification Engineer
Core
Design and develop scalable, reusable verification environments for complex consumer and automotive integrated circuits (ASICs/SoCs) using state-of-the-art verification methodologies and AI-assisted workflows.
Role type
Junior Digital Verification Engineer
Builds
Consumer and automotive integrated circuits (ASICs/SoCs)
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models
Required skills
UVM, formal verification, directed verification, VHDL/Verilog, Python/Tcl scripting, simulation/verification EDA tools, mixed-signal modeling (SystemC/MATLAB/Simulink), UPF
Preferred skills
AI-assisted engineering workflows, analog/mixed-signal modeling techniques
Responsibilities
Design and develop scalable verification environments; Apply functional and formal verification methodologies; Collaborate in a global engineering network; Document and improve verification processes; Participate in concept definition through qualification phases
Seniority
Junior, entry-level IC
