Formal verification engineer
Core
Develop formal test benches and properties to verify RTL designs using System Verilog Assertions and industry-standard formal tools.
Role type
Formal verification engineer
Builds
Verified RTL designs for Neural Network Processors (NPU), Vision DSPs, and edge AI systems
Domain
VLSI / Hardware IP / Edge AI
Deliverable
production ML models
Required skills
System Verilog, Formal Verification methodologies, RTL design verification, Verification planning, Coverage analysis
Preferred skills
Jasper, SV-UVM, Python, Tcl, Dynamic Verification
Technologies
System Verilog, Jasper, SV-UVM, Python, Tcl
Responsibilities
Write and maintain System Verilog Assertions to formally verify RTL designs; Collaborate with Design and Verification Teams; Contribute to Verification Planning and Coverage; Define formal verification plans and track progress
Seniority
Mid-level, hands-on IC
