Staff Engineer, STA
Core
Ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners.
Role type
Staff Static Timing Analysis (STA) Engineer
Builds
Block- and full-chip semiconductor designs
Domain
Semiconductor / VLSI Design
Required skills
Static Timing Analysis (STA), CMOS fundamentals, setup/hold analysis, OCV/AOCV/POCV, clock tree analysis, SDC constraints, ECO implementation, Tcl/Perl/Python scripting, Synopsys PrimeTime, Cadence Tempus
Preferred skills
Low-power timing analysis (UPF/CPF), Signal Integrity (SI) analysis, IR-drop-aware timing, automation and flow development (via careerplan.io/jobs/744000153671539-staff-engineer-sta-at-renesas-electronics)
Technologies
Synopsys PrimeTime, Cadence Tempus, Tcl, Perl, Python
Responsibilities
Perform full-chip and block-level STA across all modes and corners; Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity violations; Develop and maintain timing constraints (SDC); Drive timing closure through ECO implementation; Analyze timing impact due to process, voltage, and temperature variations; Support timing signoff for pre-layout and post-layout stages; Generate timing reports and communicate closure status.
Seniority
Senior/Staff, hands-on IC
