Sr. Manager - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
Core
Design and optimize hardware for cloud server platforms, specifically focusing on Static Timing Analysis (STA) for AWS Inferentia and other ML inference products.
Role type
Senior IC Physical Design STA Engineer
Builds
Next-generation cloud server platforms and ML inference hardware (AWS Inferentia)
Domain
Semiconductor / Cloud Infrastructure / Machine Learning Hardware
Deliverable
production ML models
Required skills
Static Timing Analysis (STA), ASIC physical design, timing constraint development, EDA tools (PrimeTime, Tempus), ECO generation, automation scripting, deep sub-micron node implementation (16nm or smaller), digital design, analog/RF layout, verification, UVM, Python, C, embedded C, low power design, SoC bring-up, post-silicon validation, parasitic extraction, circuit level analysis (SPICE/SPECTRE), IO interface timing (DDR, HBM, PCIe)
Preferred skills
RTL coding and debug, performance/power/area trade-offs, modern ASIC/FPGA design tools, advanced node expertise (16nm or below), link and system level simulation, test setup automation, CI/CD pipeline implementation, Bare Metal Environment development
Technologies
PrimeTime, Tempus, STAR-RC, Quantus, SPICE, SPECTRE, Python, C, C++, MATLAB, Perl, Git, UVM, System C
Responsibilities
Develop and maintain flows for block and full-chip level static timing analysis; Write, debug, and validate timing constraints; Run STA and provide feedback; Provide guidance on fixing timing issues (generate ECOs, fix constraints); Develop scripts to automate timing analysis and generate reports; Collaborate with RTL/Arch teams and other physical design engineers.
Seniority
Senior, hands-on IC
