Physical Design Engineer - Static Timing Analysis
Core
Develop and maintain block-level and full-chip static timing analysis flows, write and validate timing constraints, and automate analysis runs to ensure ASIC timing sign-off.
Role type
Senior IC Physical Design Engineer (Static Timing Analysis)
Builds
ASIC chips (AWS Inferentia and other cloud-scale hardware accelerators)
Domain
Semiconductor / ASIC Physical Design
Deliverable
production ML models | product features
Required skills
Static timing analysis fundamentals, timing constraint development, EDA tools (PrimeTime, Tempus), scripting (Tcl, Perl, Python), ASIC physical design flow (RTL to GDSII), IR/EM analysis, physical verification, DFT
Preferred skills
Mentoring and team leadership, building STA tool flows, ECO flows (PT-DMSA, Tempus-ECO, Tweaker), advanced process nodes (16nm or below), parasitic extraction (STAR-RC, Quantus), circuit-level analysis (SPICE, SPECTRE), IO interface timing (DDR, HBM, PCIe, Die-to-Die)
Technologies
PrimeTime, Tempus, Tcl, Perl, Python, SPICE, SPECTRE, STAR-RC, Quantus, AWS EC2
Responsibilities
Develop and maintain block-level and full-chip static timing analysis flows; write, debug, and validate timing constraints for blocks and full chips; run static timing analysis and provide feedback to teammates; advise on resolving timing issues including generating ECOs and correcting constraint problems; create scripts to automate timing-analysis runs and reporting; collaborate with physical design engineers and RTL/architecture teams; provide leadership in applying new technologies to large-scale deployments
Seniority
Senior, hands-on IC
