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Principal Package Design Engineer

San Jose, CALIFORNIA, us💼 Full-time💰 $195,000–$195,000🗓 2026-09-30 → 2026-10-02

Core

Lead the design, development, and qualification of next-generation advanced packaging solutions for high-performance semiconductors and electronic products.

Role type

Principal IC packaging engineer (advanced packaging)

Builds

High-performance semiconductor packages (Flip-chip, WLP, SiP, 2.5D/3D) for automotive, industrial, and AI/ML hardware

Domain

Semiconductor manufacturing / Advanced packaging

Required skills

Advanced packaging architecture design, thermal/mechanical reliability analysis, OSAT collaboration, failure analysis, DOE planning, cross-functional technical leadership

Preferred skills

Power semiconductor packaging (Si/SiC/GaN), chiplet-based heterogeneous integration, simulation tools (ANSYS, COMSOL, Cadence Allegro), JEDEC/IPC standards expertise

Technologies

ANSYS, COMSOL, Cadence Allegro Package Designer, JMP, Minitab

Responsibilities

Define package architecture based on electrical/thermal/mechanical requirements; lead qualification activities including failure analysis and reliability testing; develop assembly flows for OSATs; mentor junior engineers; resolve packaging issues during NPI and production ramp

Seniority

Principal, hands-on IC with strategic oversight

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