Principal Design Verification Engineer
Core
Lead verification strategy and execution for complex digital designs in next-generation semiconductor memory interface products, including data buffer silicon.
Role type
Principal Design Verification Engineer (Semiconductor)
Builds
Next-generation DDR6 memory interface products and data buffer silicon
Domain
Semiconductor / Memory Interfaces / Digital Design
Required skills
SystemVerilog, UVM, verification strategy, constrained-random verification, functional coverage, debugging, technical leadership, RTL design collaboration
Preferred skills
DDR memory experience, DDR4/DDR5 protocols, high-speed interface verification, mixed-signal verification
Technologies
SystemVerilog, UVM, DDR6, DDR4, DDR5
Responsibilities
Lead verification strategy and execution for complex semiconductor designs; Define verification methodologies, test plans, coverage strategies, and environments; Architect and optimize SystemVerilog/UVM testbenches; Drive test development, coverage closure, and debugging; Provide technical guidance and mentorship to verification engineers; Communicate verification progress and risks to leadership.
Seniority
Principal, technical leadership & hands-on IC
