Senior Principal Engineer, PD Expert (MCU and derivative devices)
Core
Senior technical authority defining Physical Design Architecture, Technology aspects, Foundry selection, and PPA for MCU and derivative devices, serving as the primary interface between the internal SoC Physical Design organization and the foundry.
Role type
Senior Principal Engineer, Physical Design Expert (MCU)
Builds
SoC and MCU designs for Automotive, Industrial, Infrastructure, and IoT applications
Domain
Semiconductor Physical Design, Embedded Systems, AI-driven cost reduction
Deliverable
production ML models | product features
Required skills
Physical Design architecture definition, Foundry selection and PPA optimization, Multi-node tapeout experience, Physical partitioning, Latency and pipeline planning, IO and AC requirement definition, Die-size and KPI alignment, AI strategy implementation for cost reduction
Preferred skills
Experience with TSMC processes, Methodology team collaboration, External vendor management
Technologies
TSMC, SoC Physical Design, AI tools for design cost reduction
Responsibilities
Serve as primary technical point of contact with TSMC for Physical Design; Lead AI initiatives to reduce MCU development costs; Define physically realizable architecture for MCU designs with system architects; Drive physical partitioning, latency, pipeline planning, IO & AC requirements; Align Die-size & PPA targets & KPI for SoC/MCUs