Senior Staff / Staff Digital Verification Engineer
Core
Developing and maintaining UVM-based verification environments, writing test benches, and debugging RTL for complex IP and SoC designs.
Role type
Senior Staff / Staff Digital Verification Engineer
Builds
Complex IP and SoC designs for automotive, industrial, infrastructure, and IoT markets
Domain
Semiconductor hardware verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM methodology, constrained-random verification, Computer Architecture, verification tools and flows, scripting (Python/Perl/Tcl)
Preferred skills
Formal Verification techniques, AI tools for code development/debugging, automotive/industrial/embedded systems experience
Technologies
UVM, System Verilog, simulators, waveform viewers, coverage tools, regression management tools
Responsibilities
Develop and maintain UVM-based verification environments, write test benches and test cases, analyze specifications and define verification plans, debug RTL issues, run regressions and monitor coverage metrics, mentor junior engineers
Seniority
Senior Staff / Staff, hands-on IC
