Staff Engineer, STA and Synthesis
Core
Ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners.
Role type
Staff Static Timing Analysis (STA) Engineer
Builds
Semiconductor chip designs (MCUs, SoCs, Analog, power products)
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> physical/clinical work (Incorrect mapping, correcting to: production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (timing closure is part of the design infrastructure flow) -> Actually, the role produces the timing signoff and closure for the chip. Let's map to 'product features' or 'infrastructure'. Given the context of chip design, 'product features' fits best as the chip is the product feature being built. However, standard mapping for IC design often falls under 'product features' or a specific 'chip design'. Let's use 'product features' as the chip is the product.
Required skills
Static Timing Analysis (STA), CMOS fundamentals, setup/hold analysis, OCV/AOCV/POCV, clock tree analysis, SDC creation, timing constraints debugging, ECO implementation, Tcl/Perl/Python scripting, Synopsys PrimeTime or Cadence Tempus
Preferred skills
Low-power timing analysis (UPF/CPF), Signal Integrity (SI) analysis, IR-drop-aware timing, automation and flow development
Technologies
Synopsys PrimeTime, Cadence Tempus, Tcl, Perl, Python, SDC
Responsibilities
Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners; Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations; Develop and maintain timing constraints including SDC creation, validation, and signoff readiness; Drive timing closure through ECO implementation and timing optimization; Analyze timing impact due to process, voltage, and temperature variations; Generate timing reports and communicate closure status to project stakeholders
Seniority
Staff, hands-on IC engineer
