Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
Core
Design and optimization of hardware for data centers, specifically focusing on static timing analysis for products like AWS Inferentia.
Role type
Physical Design Engineer (Static Timing Analysis)
Builds
Hardware chips for cloud-scale machine learning inference
Domain
Semiconductor / ASIC Physical Design
Deliverable
production ML models
Required skills
Static Timing Analysis, timing constraint development, EDA tools (PrimeTime, Tempus), ASIC Physical Design (RTL-to-GDSII), scripting (Tcl, Perl, Python), sign-off activities (IR/EM, physical verification, DFT)
Preferred skills
ECO flows, advanced nodes (16nm or below), parasitic extraction tools (STAR-RC, Quantus), circuit level analysis (SPICE/SPECTRE), IO interface timing (DDR, HBM, PCIe, Die-to-Die)
Technologies
PrimeTime, Tempus, STAR-RC, Quantus, SPICE, SPECTRE
Responsibilities
Develop and maintain flows for block and full-chip level static timing analysis; Write, debug & validate timing constraints; Run Static Timing Analysis and provide feedback; Provide guidance on fixing timing issues (generate ECOs, fix constraint issues); Develop scripts to automate running timing analysis and generate reports
Seniority
Mid-level, hands-on IC