Staff/Senior Staff Engineer, Synthesis & Timing Constraints
Core
Lead timing constraint development and synthesis methodologies for complex SoC designs to achieve high-quality implementations across advanced technology nodes.
Role type
Staff/Senior Staff ASIC/SoC Implementation Engineer
Builds
High-quality ASIC/SoC implementations for automotive, industrial, infrastructure, and IoT applications
Domain
Semiconductor (ASIC/SoC) / Digital Logic Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (SoC implementations)
Required skills
Synopsys Design Compiler, Fusion Compiler, Static Timing Analysis (STA), SDC methodology, Tcl scripting, Python scripting, advanced-node implementation flows, timing closure, area/power optimization
Preferred skills
Low-power design methodologies, Physical Design signoff flows, hierarchical/full-chip implementation, complex SoC tapeout support
Technologies
Synopsys Design Compiler, Fusion Compiler, Tcl, Python
Responsibilities
Define and maintain timing constraints (SDC) at IP, subsystem, and chip levels; Drive RTL synthesis and optimization; Analyze and resolve timing, area, and power challenges; Collaborate with cross-functional teams for design convergence; Develop automation flows to improve productivity; Support timing closure activities; Debug synthesis and timing issues.
Seniority
Senior, hands-on IC
