Senior Staff Digital Verification Engineer
Core
Verification of DDR6 Data Buffer to meet functional and performance specifications for memory interface products.
Role type
Senior Staff Digital Verification Engineer
Builds
Digital sections of leading-edge memory data buffer chips for DDR5, DDR6 and beyond
Domain
Semiconductor / Memory Interface / DDR6
Deliverable
production ML models | product features
Required skills
UVM methodology, verification planning, coverage development, testbench optimization, state-of-the-art verification environment design, feature extraction, checker development
Preferred skills
expertise in DDR6 specifications, system-level and block-level integration testing
Technologies
UVM, DDR6, DDR5
Responsibilities
Drive memory interface products verification effort including defining strategy, developing test plans, and executing tests; Work closely with design team to ensure designs meet requirements and are testable; Drive and monitor coverage of design verification; Identify and drive improvements to the verification process; Provide regular updates to management on verification status
Seniority
Senior Staff, hands-on IC
