Principal Digital Verification Engineer
Core
Develop and verify digital sections of leading-edge memory data buffer chips (DDR5, DDR6) for datacenter AI and cloud computing applications.
Role type
Principal Digital Verification Engineer (Memory Interface)
Builds
High-bandwidth, low-power memory interface chips for datacenters
Domain
Semiconductor / Memory Interface / Datacenter Infrastructure
Deliverable
production ML models | product features
Required skills
UVM methodology, System-level verification, Block-level verification, Verification planning, Coverage analysis, Testbench development, Reusable environment design, Performance optimization, Design for testability, Technical mentoring
Preferred skills
DDR5/DDR6 architecture knowledge, State-of-the-art verification techniques
Technologies
UVM, System-level tools, Block-level tools
Responsibilities
Define verification strategy, develop test plans, drive coverage monitoring, mentor verification engineers, collaborate with design teams, optimize verification processes, report status to management
Seniority
Principal, hands-on IC with mentorship
