Staff Package Design Engineer - Cu FSM/BGBM/Bumping 封装设计专家
Core
Design and develop package and interconnect methods for power SiP/modules, wafer level chip scale package, flip-chip, multi-chip module LGA, and power device packaging.
Role type
Staff Package Design Engineer (Power SiP/Flip-chip/Wafer Level)
Builds
Power SiP modules, wafer level packages, flip-chip interconnects, and multi-chip modules for automotive, industrial, and IoT applications.
Domain
Semiconductor packaging and interconnect technologies
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Cu FSM/BGBM & Bumping process expertise, wafer processing knowledge, OSAT/CM qualification, DOE execution, process integration, SPC and statistical analysis, embedded substrate technologies
Preferred skills
Embedded substrate technologies, advanced packaging roadmap development
Technologies
Cu pillar bumping, Glass carrier bonding, Taiko Backgrinding, Patterned back metal, Evaporation & Sputtering
Responsibilities
Design and develop package and interconnect methods, benchmark and qualify materials/processes/subcontractors, run DOE to optimize processes, resolve process integration issues, establish production controls, address customer complaints, develop and maintain package design rules.
Seniority
Staff, hands-on IC with strategic roadmap involvement
