Staff Engineer, Design Enablement
Core
Define and deploy physical design methodologies for advanced SOCs and MCUs across 3/5/16/22nm nodes.
Role type
Staff Engineer, Physical Design Methodology
Builds
Physical design flows and tool configurations for SoCs/MCUs
Domain
Semiconductor / VLSI / Physical Design
Required skills
Physical Design (Floorplan, Power-plan, Place & Route, UPF, CTS), EDA tools (Synopsys Fusion Compiler, Cadence Innovus), Scripting (Perl, TCL, Python), Low power optimization, Timing convergence
Preferred skills
Cross-functional collaboration, Vendor management, Flow automation
Technologies
Synopsys Fusion Compiler, Cadence Innovus, Perl, TCL, Python
Responsibilities
Develop physical design methodology for advanced geometry nodes, Manage requirements for Place & Route/UPF/Formal Verification/Floorplan, Evaluate and benchmark EDA vendor tools, Resolve blocking issues with EDA vendors, Deploy new tools and methodologies organization-wide
Seniority
Staff, hands-on IC with strategy & mentorship
