Senior ASIC layout design engineer_BST
Core
Senior ASIC layout design engineer responsible for analog layout from block to top-level IC integration and physical verification for advanced ASICs in MEMS sensors.
Role type
Senior IC analog layout engineer
Builds
Advanced ASICs for MEMS sensors
Domain
Semiconductor manufacturing / MEMS sensors
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog/mixed-signal IC layout, Floorplanning, DRC/ERC/ANT/LVS analysis, Scripting (C shell, SKILL, TCL, Python), Cadence Virtuoso, Process side effect mitigation (lithographic mismatch, LOD, WPE, latch-up, ESD, antenna, density stress), EM and IR drop analysis
Preferred skills
Experience with TSMC28nm-152nm, SMIC110nm, TZ 180nm BCD SOI technologies
Technologies
Cadence Virtuoso, Calibre, PVS, Assura
Responsibilities
Execute tape-out flow with wafer foundry, Collaborate with digital backend engineers for DFE generation, Work with CAD engineers to improve PDKs and design environment, Analyze PLS results and provide optimization solutions
Seniority
Senior, hands-on IC
