Director of ASIC Design Verification
Core
End-to-end verification leadership for next-generation RDU chips (machine learning ASICs), covering block through full-chip verification, performance validation, and first-silicon bring-up.
Role type
Director of ASIC Design Verification (hands-on technical authority + team leadership)
Builds
High-performance machine learning ASICs (RDU chips) for enterprise and government generative AI platforms
Domain
Semiconductor / Machine Learning Hardware / ASIC Design
Deliverable
production ML models (via hardware validation)
Required skills
ASIC design verification, SystemVerilog, SVA, Python, UVM/OVM/VMM, performance verification, emulation, FPGA prototyping, first-silicon debug, verification architecture strategy, team leadership (8-10 engineers)
Preferred skills
MS/PhD in EECS, 15+ years experience, high-performance interconnect protocols (PCIe, Ethernet), memory subsystems, advanced TSMC nodes, chiplet verification, AI-assisted verification workflows
Technologies
SystemVerilog, SVA, Python, UVM, OVM, VMM, FPGA, Emulation platforms, EDA tools
Responsibilities
Define verification architecture and strategy for complex ML ASICs; own pre-silicon quality, coverage closure, and tape-out readiness; lead debug on hardest pre-silicon failures; support lab functional validation and bring-up debug for first silicon; lead and grow a team of principal-level verification engineers; evolve the verification environment and methodology; partner with architecture, design, and software teams on requirements and validation
Seniority
Director, hands-on IC with management responsibilities
