Sr Digital Design Engineer
Core
Designing and implementing RTL for complex DRAM digital and mixed-signal blocks to meet PPA objectives.
Role type
Senior IC digital design engineer (ASIC/RTL)
Builds
Next-generation memory products (DRAM)
Domain
Semiconductor / Memory / Digital ASIC
Required skills
RTL design (Verilog/SystemVerilog), logic synthesis, static timing analysis (STA), CDC/RDC analysis, UPF-based power intent, SDC constraint development, PPA optimization
Preferred skills
Memory product RTL experience, CMOS digital/mixed-signal concepts, cross-functional collaboration, engineering automation
Technologies
Verilog, SystemVerilog, SDC, UPF
Responsibilities
Develop RTL for DRAM blocks, perform front-end design quality checks (linting, synthesis, timing closure), collaborate with architecture/verification/physical design teams, develop timing constraints, improve design methodologies and automation
Seniority
Senior, hands-on IC
