PRINICPAL RTL DESIGN
Core
Lead the full RTL design lifecycle for high-quality DRAM digital and mixed-signal IP, delivering designs that meet aggressive PPA targets.
Role type
Principal RTL Design Engineer (DRAM IP)
Builds
DRAM digital and mixed-signal IP cores
Domain
Semiconductor / Memory / ASIC Design
Required skills
RTL design, logic synthesis, static timing analysis (STA), UPF-based power intent, CDC/RDC, Verilog/SystemVerilog, ASIC low-power design methodologies
Preferred skills
DRAM architecture, mixed-signal interfacing, CMOS digital/analog concepts, Agentic AI
Technologies
Verilog, SystemVerilog, UPF, CDC, RDC, STA
Responsibilities
Own and drive RTL design from specification through silicon-ready signoff; Architect high-performance, power- and area-efficient RTL designs; Perform and sign off front-end quality checks (lint, CDC/RDC, synthesis, UPF, timing QoR); Collaborate with physical design, verification, and architecture teams; Improve design quality and efficiency by refining methodologies and automation.
Seniority
Principal, technical leadership
