SrvDigital Design Engineer
Core
Design and implement RTL for complex DRAM digital and mixed-signal blocks, ensuring alignment with product specifications and performance targets.
Role type
Senior IC digital design engineer (ASIC/RTL)
Builds
High-performance, power-efficient DRAM digital and mixed-signal blocks for next-generation memory products
Domain
Semiconductor / Memory / Digital ASIC
Required skills
RTL design (Verilog/SystemVerilog), logic synthesis, static timing analysis (STA), CDC/RDC analysis, UPF-based power intent, SDC constraint development, PPA optimization
Preferred skills
Memory product RTL design, CMOS digital and mixed-signal circuit concepts, cross-functional collaboration, engineering automation
Technologies
Verilog, SystemVerilog, SDC, UPF, Linting tools, Simulation tools
Responsibilities
Design and deliver RTL for complex DRAM digital and mixed-signal blocks; Perform front-end design quality checks including linting, CDC/RDC analysis, logic synthesis, and timing closure; Collaborate with architecture, verification, and physical design teams to optimize PPA; Develop and maintain synthesis and timing constraints; Improve design methodologies and RTL-to-GDS flows
Seniority
Senior, hands-on IC
